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PRELIMINARY
CY3144
Cypress Mentor Graphics Bolt-in Kit
Features
* * * * * * * * Seamless integration with your Mentor Graphics tools Powerful schematic symbol library IEEE-compliant VHDL Supports the UltraLogicTM family of SPLDs and CPLDs Industry-leading synthesis for programmable logic 100% automatic fitting VHDL and Verilog post-layout timing models Complete solution from design entry to programming
System Requirements
For Sun Workstations SPARC CPU SunOS 4.1.3 or Solaris 2.5 CD-ROM drive For HP 9000 workstation (700 series) HP-UXTM 9.x CD-ROM drive
Introduction
Cypress offers powerful integrated solutions for programmable logic. The Cypress Mentor Graphics Bolt-in Kit gives you everything to design with Cypress's UltraLogic PLDs in one seamless device-independent design environment. It allows you to take advantage of Mentor Graphics' powerful Design ArchitectTM schematic entry tool, Cypress's industry-leading WarpTM VHDL synthesis tool, and a wide variety of simulators.
Ordering Information
CY3144 Cypress Mentor Graphics Bolt-in Kit includes: CD-ROM with Bolt-in software and on-line documentation CD-ROM with Warp software and on-line documentation Warp User's Guide and Reference Manual Release Notes VHDL for Programmable Logic Textbook
Functional Description
Design Entry Design with ease using schematic symbols, VHDL design descriptions, or a combination of both, supported with the Mentor Design Architect tool available with your Mentor flow. Synthesis Your entire design is automatically converted into VHDL and efficiently synthesized into a SPLD or CPLD device using Warp. UltraGenTM synthesis technology will ensure that you achieve the best results for every Cypress device. For a description of UltraGen and synthesis, see the Warp datasheets. Fitting Easily retarget your design to different devices. The 100% automatic fitting tools produce optimal results in minutes. Post-synthesis Simulation
Text
Sch
Design Flow Manager
Synthesis
Fitting
Program File
Warp outputs VHDL and Verilog timing simulation models. Verify your design with timing using your choice of Mentor Graphics' QuickHDLTM or any other VHDL or Verilog simulator.
Programming
Simulation
Warp generates JEDEC programming files for all Cypress devices which can be used for in-system reprogramming (ISRTM) or with various device programmers.
Document #: 38-00593
Available from Cypress Available from Mentor Graphics
Figure 1. Cypress Mentor Graphics Design Flow
HP-UX is a trademark of Hewlett Packard Corporation. SunOS and Solaris are trademarks of Sun Microsystems Corporation. Design Architect, and QuickHDL are trademarks of Mentor Graphics Corporation. ISR, UltraGen, UltraLogic, and Warp are trademarks of Cypress Semiconductor Corporation
Cypress Semiconductor Corporation
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3901 North First Street
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San Jose
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CA 95134
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408-943-2600 March 28, 1997

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